In wireless transmission of data the error rate of received data is relatively high, due to many factors including, for example, interference. To improve the performance of wireless communication systems data to be transmitted is encoded using an error correction code that can be recovered by the receiver.
One technique discussed in the related art to decode data is a low density parity check (LDPC) encoding which is based on an LDPC code. The LDPC code utilizes a sparse parity check matrix. In LDPC coding, the sparse parity matrix can be generated either randomly or by algebraic methods and subject to predefined constraints.
FIG. 1 shows a schematic diagram of a signal-carrier modulation transmitter 100 that performs LDPC encoding. The transmitter 100 includes a scrambler 110 for scrambling the bits of an input data word using a polynomial function, a repetition unit 120 that duplicates the scrambled input word, and a linear feedback shift register (LFSR) 130 for scrambling the output of the repetition unit 120 to generate a scrambled repeated word.
The transmitter 100 also includes an LDPC encoder 140 of rate 1/k (k=2 or 4) having a code length of N (N is an integer number). The inputs to the LDPC encoder 140 are the scrambled repeated data word and the scramble input data word, each data word is in length of N/4 bits. The LDPC encoder 140 must receive a word in a length that is twice that of the length of the input data word. The LDPC encoder 140 computes the parity bits (2/N bits) using a parity matrix and outputs an encoded codeword having a length of N bits. The encoded codeword is modulated using a signal carrier modulator 150 and transmitted over a wireless medium to a receiver.
The receiver should decode the received signal using an LDPC decoder. In order to properly decode the signal, the decoder should have an indication on the location of the scrambled input data word and the scrambled repeated data word in the received signal. This complicates the implementation of the receiver as it requires additional hardware and a modified LDPC decoder to distinguish between the different data words. FIGS. 2A, 2B and 2C show block diagrams of different conventional implementations of signal-carrier modulation receivers.
The receiver 200 shown in FIG. 2A includes a standard LDPC decoder 201 of 1/k rate that requires two different channels 202 and 203 in order to perform error checking of one each of the scrambled input data word and the scrambled repeated data word included in the received signal. The output of the channel with a minimum number of errors is selected. The implementation of the receiver 200 is relatively simple, but it suffers from poor performances (e.g., a high error rate).
The receiver 210 shown in FIG. 2B consists of a maximum ratio combining (MRC) unit 213 that combines the scrambled input data word and the scrambled repeated data word. The input to the LDPC decoder 214 are two data words, each of which having a length of N/2 and the parity matrix. The receiver 210 also includes two channels 211 and 212 to error check the data word included in the received signal. Although the receiver 210 provides improved performance in comparison to the receiver 200, still its error rate when decoding received signals is relatively high. In addition, two channels and a MRC unit are needed to implement the receiver 210.
The receiver 220 depicted in FIG. 2C provides optimal performance in terms of error rates, but necessitates implementing a modified LDPC decoder 221 with a shorten LDPC code (e.g., 3N/4 instead of N). This is a costly approach as it requires designing a receiver with non-standard decoders and other components.
It would be therefore advantageous to provide a solution that would limit the drawbacks of existing LDPC coding based receivers and transmitters.